1. Field of the Invention
The present invention relates to substrate processing, and more particularly to improving the substrate processing using optimized gate channel procedures and subsystems.
2. Description of the Related Art
Current low cost products use a bulk silicon technology. As the transistor continues to shrink, the impact of the channel depth is becoming critical (ultra-shallow source/drain extensions). As the silicon-on-insulator (SOI) firm shrinks, a small variation in the gate oxide swelling becomes a larger percent of the SOI firm thickness. The resultant increase in the variation of thickness of the SOI film both at the edge of the gate and over the contact areas affects the conductive properties of the contact of the source and drain. When gate-etch procedures are not controlled, the removal of the exposed gate oxide near the gate affects the electric field between the source and drain.
Current high performance microprocessors from device manufacturers, such as International Business Machines (IBM) and Advanced Micro Devices (AMD) use PD SOI (partially depleted film having a threshold voltage 0.2 volts and C of 0.7), PD SOI films are around 50 nm while the oxide swelling can be 5 nm (or 10% of the thickness).
Future generations of SOS films are called FD SOI (fully depleted firm having a threshold voltage 0.08 volts and a thickness of ˜25 nm). Currently these films are not in production due to limitations in thickness control uniformity and defects. Channel mobility degrades with decreasing SOI thickness. Using the current procedures would allow the gate oxide swelling to continue, and the current results can be as large as 20% of the SOI thickness.
With thinner SOI film, the impact of the spacer sidewall thickness also becomes a critical knob to control due to its impact on the implant profile.